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HardCopy Designer Curriculum

This curriculum is designed for hardware engineers with experience designing ASICs and who are familiar with VHDL or Verilog HDL. These engineers are targeting a HardCopy® ASIC.

Table Legend
  Required if no prior experience
  Optional
  Suggested

Instructor-led Training Online Training
The Quartus® II Software Design Series: Foundation
(IDSW110)

(8 hours)
The Quartus II Software Interactive Tutorial
(ODSW1050)

(4 hours)
The Quartus II Software Design Series: Timing Analysis
(IDSW120)

(8 hours)
Using the Quartus II Software: An Introduction
(ODSW1100)

(1.5 hours)
简体中文
(OCDSW1100)
or The Quartus II Software Design Series: Foundation
(ODSW1110)

(8 hours)
简体中文
(OCDSW1110)
The Quartus II Software Design Series:
Verification
(IDSW130)

(8 hours)
I/O Management
(ODSW1107)

(1 hour)
The Quartus II Software Design Series: Optimization
(IDSW140)

(8 hours)
TimeQuest Timing Analyzer
(ODSW1115)

(1.5 hours)
简体中文
(OCDSW1115)
Designing with HardCopy II Devices
(IHC210)

(8 hours)
What’s New in the Quartus II Software Version 8.0
(ODSW1103)

(1 hour)
HardCopy II Architecture and Design Flow
(OHC1110)

(1.5 hours)
HardCopy II Devices: Design Guidelines
(OHC1120)

(1 hour)
Power Analysis with the Quartus II Software
(ODSW1146)

(1 hour)
Using High-Performance Memory Interfaces in Altera® FPGAs
(OMEM1110)

(1.5 hours)
Constraining and Analyzing Timing for Source Synchronous Circuits with TimeQuest
(ODSW1160)

(1 hour)
Constraining and Analyzing Double Data Rate Source Synchronous Interfaces
(OMEM1120)

(1 hour)

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