Introduction to VHDL
(IHDL110)
(8 hours) |
or |
Introduction to Verilog HDL
(IHDL120)
(8 hours) |
Basics of Programmable Logic
(ODSW1005)
(1 hour) |
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The Quartus® II Software Design Series: Foundation
(IDSW110)
(8 hours) |
How to Begin a Simple FPGA Design
(ODSW1010)
(0.5 hours) |
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The Quartus II Software Design Series: Timing Analysis
(IDSW120)
(8 hours) |
VHDL Basics
(OHDL1110)
(1 hour) |
or |
Verilog HDL Basics
(OHDL1120)
(1 hour) |
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The Quartus II Software Design Series:
Verification
(IDSW130)
(8 hours) |
The Quartus II Software Interactive Tutorial
(ODSW1050)
(4 hours) |
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Interfacing to External Memory with Altera FPGAs
(IMEM210)
(8 hours) |
Using the Quartus II Software: An Introduction
(ODSW1100)
(1.5 hours)
简体中文
(OCDSW1100)
|
or |
The Quartus II Software Design Series: Foundation
(ODSW1110)
(8 hours)
简体中文
(OCDSW1110) |
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The Quartus II Software Design Series: Optimization
(IDSW140)
(8 hours) |
Using the Quartus II Software: Schematic Design
(ODSW1105)
(0.5 hours)
简体中文
(OCDSW1105) |
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Advanced VHDL Design Techniques
(IHDL240)
(8 hours) |
or |
Advanced Verilog HDL Design Techniques
(IHDL230)
8 hours) |
I/O Management
(ODSW1107)
(1 hour) |
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TimeQuest Timing Analyzer
(ODSW1115)
(1.5 hours)
简体中文
(OCDSW1115) |
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What’s New in the Quartus II Software Version 8.0
(ODSW1103)
(1 hour) |
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Early Pin Planning with Pin Planner in the Quartus II Software
(ODSW1112)
(0.5 hours) |
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Overview of Mentor Graphic’s ModelSim Software
(ODSW1120)
(1 hour) |
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Switching to the TimeQuest Timing Analyzer
(ODSW1125)
(1 hour) |
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Stratix III Devices: Features and Capabilities
(OSIII1110)
(1 hour) |
or |
Cyclone III Devices: Features and Capabilities
(OCIII1110)
(1 hour) |
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Design Planning Guidelines for High-Density FPGAs
(ODSW1130)
(1 hour) |
| |
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Introduction to Incremental Compilation
(ODSW1136)
(2 hours) |
Power Analysis with the Quartus II Software
(ODSW1146)
(1 hour) |
Using the Quartus II Software: Managing Design Changes with Chip Editor
(ODSW1152)
(1 hour) |
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Design Partition Planner in the Quartus II Software
(ODSW1138)
(1 hour) |
Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction
(OVJTAG1110)
(0.5 hours) |
Using the Quartus II Software: Chip Planner
(ODSW1155)
(1 hour) |
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Best Practices for Incremental Compilation Partitions and Floorplan Assignments - Part 1 of 2
(ODSW1143)
(1 hour) |
Serial RapidIO Design with Stratix IV GX FPGAs
(ORIO1115)
(1.5 hours) |
Using High Performance Memory Interfaces in Altera FPGAs
(OMEM1110)
(1.5 hours) |
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Best Practices for Incremental Compilation Partitions and Floorplan Assignments - Part 2 of 2
(ODSW1144)
(1 hour) |
FPGA to Board Design Flow Using Mentor Graphics Tools
(ODSW1170)
(1.5 hours) |
Constraining and Analyzing Timing for Source Synchronous Circuits with TimeQuest
(ODSW1160)
(1 hour) |
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SignalTap II Embedded Logic Analyzer
(ODSW1164)
(1.5 hours)
简体中文
(OCDSW1165) |
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Constraining and Analyzing Double Data Rate Source Synchronous Interfaces
(OMEM1120)
(1 hour) |
Literature
> 
