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Home > Education & Events > Course Print This Page Subscribe to Email Best Practices for Incremental Compilation Partitions and Floorplan Assignments - Part 2 of 2 (ODSW1144) 1 Hour Online Course Course Description This training will explain why and when to create a design floorplan for incremental compilation. You will learn how to create a floorplan, and follow guidelines to create an optimal floorplan for your design partitions. You will also learn about the Quartus® II tools available to help create a design floorplan. Finally, you will learn about limitations and restrictions with the incremental compilation feature in the Quartus II software version 7.2. At Course Completion Create good floorplan assignments for your design partitions, when required Use helpful software tools to help you analyze your partitions and floorplan assignments Identify restrictions and limitations that may apply to your design, with the Quartus II software version 7.2 Prerequisites We recommend completing the following courses: Best Practices for Incremental Compilation Partitions and Floorplan Assignments - Part 1 of 2 Using the Quartus II Software: An Introduction Skills Required Basic understanding of FPGA logic design Basic understanding of the Quartus II user interface and incremental compilation Applicable Training Curriculum This course is part of the following Altera training curriculum: Asic-to-FPGA Designer FPGA Designer Class Schedule Result Showing 1 Location Dates Price   On-line Any Time Free Register Now Request a class in your region Rate This Page

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