Course Description
The design partition planner allows you to see how your design blocks are inter-related and illustrate the data flow in your design. In this training, you will learn to make informed design partition choices and achieve better results. You will see a demonstration of the graphical interactive environment for creating and experimenting with partitions. The Quartus® II software version 8.0 will be used for demonstration purposes.At Course Completion
- Decide when to use the design partition planner
- Using the design partition planner in conjunction with other Quartus II software features such as incremental compilation and the chip planner
- Management of design partitions
- Using the data provided to change partitions
Prerequisites
We recommend completing the following courses:- Introduction to Incremental Compilation
- The Quartus II Software Interactive Tutorial
- Using the Quartus II Software: An Introduction
Skills Required
- Background in digital logic design
- An understanding of basic FPGA design flow
- Completion of the "Using the Quartus II Software: An Introduction" online training course OR
- Completion of the tutorial available in the Quartus II software online help OR
- A solid working knowledge of the Quartus II software
- Familiarity with the incremental compilation methodology
Applicable Training Curriculum
This course is part of the following Altera training curriculum:Class Schedule
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