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The Quartus II Software Design Series: Optimization
(IDSW140)
8 Hours
Instructor-Led Course
Course Description
You will learn advanced features of the Quartus® II design software v.8.0 that will enable you to shorten your design cycle as well as improve your design performance and utilization. You will use the incremental compilation flow and LogicLock™ regions in the Quartus II software to reduce compile times and preserve performance on selected regions of your designs. You will obtain your design goals in the area of performance, resource usage and power consumption by using design strategies, HDL coding styles and Quartus II software settings. You will also learn how to manage compile times effectively.
At Course Completion
- Define physical region constraints for an FPGA design using LogicLock regions
- Manage user-defined design partitions using the Quartus II incremental compilation flow
- Apply incremental compilation to the top-down & bottom-up design flows
- Use Quartus II software settings to improve internal & I/O timing, reduce logic resource usage & lower power consumption
- Choose recommended HDL coding styles
- Run Design Space Explorer to select optimal setting for full or partial designs
Prerequisites
We recommend completing the following courses:
Skills Required
- Experience with PCs and the Windows operating system
- Completion of "The Quartus II Software Design Series: Foundation" course OR a working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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