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The Quartus II Software Design Series: Timing Analysis
(IDSW120)
8 Hours
Instructor-Led Course
Course Description
You will learn how to constrain & analyze a design for timing using the TimeQuest timing analyzer in the Quartus® II software v. 8.0. This includes understanding FPGA timing parameters, writing Synopsys Design Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.
At Course Completion
- Perform basic timing analysis with TimeQuest
- Create all required timing constraints (clock, I/O, multicycle, false paths) to fully constrain your FPGA design
- Write & manipulate SDC files for analysis & to control the compilation
- Apply timing constraints to the design to guide the Fitter to meet timing requirements
- Analyze timing with detailed TimeQuest reports
Prerequisites
We recommend completing the following courses:
Skills Required
- Experience with PCs and the Windows operating system
- Completion of "The Quartus II Software Design Series: Foundation" online or instructor-led course OR a working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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