| Table 1. Demonstration Topics |
| Quartus II Topic |
Online Demonstration Modules |
| Quartus II Software Overview |
- Compile your first design using Quartus II Software
- Introductory information about Quartus II Software
|
| Basic FPGA/CPLD Design |
- Design entry
- Compilation
- TimeQuest Timing Analyzer
- Simulation
- Programming
- Scripting
|
| Design Flows |
- MAX+PLUS® II project conversion to Quartus II Software
- MAX+PLUS II user interface
- System design using SOPC Builder
- Importing custom peripherals into SOPC Builder
- Creating multi-clock domain systems
- Designing for HardCopy® II ASICs
- Nios® II Processor C-to-Hardware (C2H) acceleration compiler
|
| Design Optimization and Implementation |
- Integrated cross probing
- Optimization advisors which provide design-specific suggestions to improve design results
- Register transfer level (RTL) viewer and technology map viewer to check synthesis and fitting results
- I/O assignment analysis to validate pin assignments early
- Timing closure floorplan
- Netlist optimization to improve push-button results
- Design space explorer to increase design performance
|
| Reducing Design Cycles |
- Incremental compilation and team-based design
- Integrated cross probing
- Using I/O assignment analysis to validate pin assignments early
|
| Verification |
- TimeQuest timing analyzer
- Analyzing and optimizing power in FPGAs
- Update FPGA memory contents in-system to facilitate verification
- Perform a functional and/or a timing simulation with the Model TechnologyTM ModelSim®-Altera software
|
Literature
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