For Release: May 19, 2008
Altera’s Quartus II Software Version 8.0 Delivers Unprecedented Performance and Productivity for High-End FPGAs
Performance, Logic Utilization and Compile-Time Advantages Enable Fastest Time to Market and Efficient Team-Based Design
San Jose, Calif., May 19, 2008—Continuing its leadership position in design software performance and productivity, Altera Corporation (NASDAQ: ALTR) today announced its Quartus® II software version 8.0, supporting the company’s 40-nm Stratix® IV FPGAs and HardCopy® ASICs. This version of the Quartus II software delivers, on average, a full two-speed grade advantage and 3X faster compile times for high-end FPGAs when compared to the nearest competitor’s latest offering. With new productivity features and support for the industry’s most advanced FPGAs, version 8.0 reinforces Altera’s commitment to deliver the highest level of performance and productivity to FPGA designers. (See related announcement “Altera Announces Industry’s First 40-nm FPGAs and HardCopy ASICs").
Over the past five years, Quartus II software has consistently delivered the industry’s fastest compile times for high-end FPGAs, averaging a 20 percent reduction annually. Customers using the 8.0 release to design Altera’s 65-nm Stratix III FPGAs on Windows platforms will see compile times reduced by up to 50 percent, with an average reduction of 22 percent, when compared to version 7.2. Users of Linux platforms will see average compile times decrease by more than 30 percent. Designs leveraging multiprocessor-based servers will obtain an even higher compile time advantage—an additional 20 percent reduction on average—using the industry’s only vendor-supplied FPGA design software with multiprocessor support.
Second-to-None Productivity Advantage
Quartus II software’s incremental compilation feature offers users a second-to-none productivity advantage, capable of delivering up to a 70 percent compile time reduction compared to a standard compilation. Assisting designers in maximizing the full benefits that incremental compilation provides, Quartus II software version 8.0 features a new design partition planner. During the process of creating incremental compilation design partitions, an interactive graphical user interface (GUI) provides real-time feedback, such as logic resource usage and inter-partition timing paths, enabling designers to explore and quickly determine the most effective partition scheme.
“Our customers continue to emphasize the importance of FPGA design productivity in the race to get products to market,” said Chris Balough, marketing director for software, embedded, and DSP at Altera. “With the release of version 8.0, Altera continues to earn our customer’s confidence that they have a clear productivity advantage with Quartus II software, which they can now leverage for the industry’s most advanced 40-nm FPGAs.”
Additional Enhancements to Quartus II Software Version 8.0
- New tasks window: Provides an interactive design flow console that guides users through the FPGA design flow.SOPC Builder: Offers support for incremental compilation and adds key intellectual property (IP) blocks to its design library, including JTAG and SPI interfaces.
- Enhanced FPGA I/O planning: Accelerates board development with added pin-swapping capabilities in the Pin Planner.
- New IP advisor: Provides design-specific guidelines and recommendations for successful use of Altera’s PCI Express and DDR3 IP.
- MegaCore® IP Library: Integrated in Quartus II software, making it easier for users to access Altera’s portfolio of IP cores. New additions with this release include PCI Express Gen2 hard IP, five new video and image processing cores and many feature enhancements.
- New megafunctions: New floating point, delay lock loop and memory initialization megafunctions in Quartus II software help speed design development.
For further information about the features offered in Quartus II software version 8.0, visit www.altera.com/q2whatsnew.
Pricing and Availability
Quartus II Subscription Edition software version 8.0 is available now through local Altera® sales representatives and distributors. Both the subscription edition and the web edition of Quartus II software version 8.0 will be available for download on June 2 at www.altera.com/download. Quartus II software is also available in DVD format by request at www.altera.com/dvdrequest. Altera’s software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II Subscription Edition software, the Mentor Graphics® ModelSim®-Altera edition and a full license to the IP Base Suite, which includes 11 of Altera’s most popular IP (DSP and memory) cores. The annual software subscription is $2,495 for a node-locked PC license and can be purchased at www.altera.com/buyquartus.
About Altera
Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more at www.altera.com.
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